Generally, in an insulated type power semiconductor module used in a power conversion device such as an inverter or a converter, a wiring pattern is formed on an insulating layer provided on a metal plate which serves as a heat radiation plate, and power semiconductor elements such as transistors and diodes are provided on the wiring pattern. Then the power semiconductor elements are connected to an external terminal or the like by wire bonding and sealed with resin, for example.
In order to obtain a power semiconductor module which performs switching operation at a large current, the module is provided with a plurality of semiconductor elements operating in parallel. However, even when the plurality of semiconductor elements operating in parallel have equivalent characteristics to each other, due to different wiring in the module, the switching characteristics may become different when the plurality of semiconductor elements are made to operate in parallel. As the number of semiconductor elements operating in parallel increases, the footprint of each element increases and the wiring becomes complicated, which increases the parasitic inductance between the plurality of semiconductor elements operating in parallel.
Due to the variation on operation of the plurality of semiconductor elements operating in parallel and the increase of the parasitic inductance between the elements, an oscillation may occur. The oscillation is called as “gate oscillation” which is caused by the parasitic capacitance of the semiconductor elements and the parasitic inductance between the elements. The gate oscillation may cause the semiconductor elements to degrade or breakdown, and may also cause noises to be radiated to the outside of the module or cause conductive noises in the external circuit, for example.
It is known that the gate oscillation may be suppressed by connecting a resistor in series to a gate wiring of a semiconductor element as described in PTL 1 (see PTL 1). PTL 2 discloses that the gate oscillation may be suppressed by connecting a resistor in parallel to an emitter wiring of the plurality of semiconductor elements connected in parallel (see PTL 2).
On the other hand, as a measure for reducing the variation on switching characteristics that causes the gate oscillation, PTL 3 discloses a technique of adjusting the inductance and resistance of the emitter wiring of a plurality of semiconductor elements connected in parallel so as to suppress the current imbalance between the elements (see PTL 3). Further, PTLs 4 to 6 disclose a technique of reducing the current imbalance, noise or oscillation between elements by coupling a gate wiring and an emitter wiring to a magnet in such a manner that the gate wiring and the emitter wiring are configured to pass through a ferrite core of the magnet (see PTLs 4 to 6).